I. Field
The present disclosure relates generally to electronics, and more specifically to a combinatorial circuit having shorter delay.
II. Background
A combinatorial circuit/logic is a digital circuit that receives input signals and generates output signals without utilizing a clock. Whenever the input signals change, the output signals can change after a certain delay. This delay is dependent on the circuitry used to implement the combinatorial circuit, and the circuitry may in turn be dependent on the complexity of a logic function being implemented by the combinatorial circuit. In general, more input signals and/or greater complexity of the logic function may result in more levels of circuitry, which may then result in longer delay for the combinatorial circuit.
A combinatorial circuit may be used with sequential circuits, which are circuits that are triggered by a clock. For example, the combinatorial circuit may receive its input signals from one sequential circuit and may provide its output signals to another sequential circuit. In this case, the speed at which the sequential circuits can operate may be dependent on the delay of the combinatorial circuit. In general, progressively higher clock rate may be used for the sequential circuits with progressively shorter delay for the combinatorial circuit. Hence, it may be desirable to reduce the delay of the combinatorial circuit in order to support a higher clock rate for the sequential circuits.